The field effect transistor (FET) is a common element of an IC. In general, when fabricating multiple FETs of similar size, it is desired that a performance characteristic such as threshold voltage (Vt) be matched between devices. In general, the Vt tends to decrease in response to reduced gate length. As gate electrode lengths approach dimensions less than 100 nanometers (nm), what is seen is that the Vt drops off or decreases rapidly. Therefore, even a small change in the gate electrode length (e.g., a 10 nanometer difference from a targeted length), can significantly affect the Vt.
Ideally, the Vt should be constant over a range of gate lengths about a target gate length to account for manufacturing margins. To promote a more constant Vt over a range of acceptable gate lengths, locally implanted dopants (p-type for NMOS devices and n-type dopants in PMOS devices) may be introduced under the gate edges. Such implants are referred to as “halo” or “pocket” (hereafter “halo”) implants. The implanted dopant tends to raise the dopant concentration around the edges of the channel, thereby increasing the Vt. One effect is to reduce the Vt of the target size device while maintaining the Vt of the worst case size device.
Typical halo implants for NMOS devices generally include boron (e.g., by implanting boron fluoride (BF2)), or indium (In)). Halo implants for PMOS devices generally include arsenic, antimony, and phosphorous. With respect to NMOS devices, In can be a particularly effective dopant because In generally forms a retrograde profile from the surface of the device. Such a concentration profile with respect to In tends to decrease the threshold voltage required to meet a given leakage current (Ioff) relative to a device having a boron dopant which does not provide the same retrograde profile.